This week on the IEEE Digital Elements and Packaging Know-how Convention, Intel unveiled that it’s creating new chip packaging expertise that can enable for larger processors for AI.
With Moore’s Legislation slowing down, makers of superior GPUs and different knowledge heart chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most dimension of a single silicon chip is mounted at round 800 sq. millimeters (with one exception), in order that they’ve needed to flip to superior packaging applied sciences that combine a number of items of silicon in a approach that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC have been aimed toward tackling limitations in simply how a lot silicon you possibly can squeeze right into a single bundle and the way large that bundle will be. They embrace enhancements to the expertise Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct methodology for bonding silicon to the bundle substrate, and system to increase the dimensions of a essential a part of the bundle that take away warmth. Collectively, the applied sciences allow the combination of greater than 10,000 sq. millimeters of silicon inside a bundle that may be larger than 21,000 mm2—an enormous space concerning the dimension of 4 and a half bank cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single bundle has to do with connecting a lot of silicon dies at their edges. Utilizing an natural polymer bundle substrate to interconnect the silicon dies is probably the most reasonably priced possibility, however a silicon substrate means that you can make extra dense connections at these edges.
Intel’s resolution, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural bundle beneath the adjoining edges of the silicon dies. That sliver of silicon, known as EMIB, is etched with nice interconnects that improve the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the newest twist on the EMIB expertise, known as EMIB-T. Along with the same old nice horizontal interconnects, EMIB-T gives comparatively thick vertical copper connections known as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board beneath to straight hook up with the chips above as a substitute of getting to route across the EMIB, lowering energy misplaced by an extended journey. Moreover, EMIB-T incorporates a copper grid that acts as a floor aircraft to scale back noise within the energy delivered resulting from course of cores and different circuits abruptly ramping up their workloads.
“It sounds easy, however this can be a expertise that brings quite a lot of functionality to us,” says Rahul Manepalli, vice chairman of substrate packaging expertise at Intel. With it and the opposite applied sciences Intel described, a buyer may join silicon equal to greater than 12 full dimension silicon dies—10,000 sq. millimeters of silicon—in a single bundle utilizing 38 or extra EMIB-T bridges.
Thermal management
One other expertise Intel reported at ECTC that helps improve the dimensions of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the expertise used at present to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they are going to hook up with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the bundle’s interconnects to the silicon’s.
As a result of the silicon and the substrate increase at completely different charges when heated, engineers must restrict the inter-bump distance, or pitch. Moreover, the growth distinction makes it troublesome to reliably make very massive substrates filled with numerous silicon dies, which is the route AI processors must go.
The brand new Intel tech makes the thermal growth mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates will be populated with dies. Alternatively, the identical expertise can be utilized to extend the density of connections to EMIB all the way down to about one each 25 micrometers.
A flatter warmth spreader
These larger silicon assemblages will generate much more warmth than at present’s methods. So it’s essential that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of steel known as a warmth spreader is essential to that, however making one large enough for these massive packages is troublesome. The bundle substrate can warp and the steel warmth spreader itself may not keep completely flat; so it may not contact the tops of the recent dies it’s imagined to be sucking the warmth from. Intel’s resolution was to assemble the built-in warmth spreader in components as a substitute of as one piece. This allowed it so as to add additional stiffening elements amongst different issues to maintain all the things in flat and in place.
“Protecting it flat at greater temperatures is an enormous profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nevertheless, they are going to possible must arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s deliberate packaging growth.
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